Lead Analog ASIC Systems Design Engineer

We are seeking a technically driven Analog ASIC Systems Design Engineer to lead systems engineering efforts across concept development, architecture definition, and design implementation for cutting-edge research and technology maturation. This role blends system-level thinking with deep hands-on ASIC design experience (analog and digital).

Ideal candidates will bring a 70/30 mix of design/implementation and systems engineering skills and have led full product lifecycles-from concept through architecture, design, tape-out, and validation. Success in this role requires comfort navigating low-TRL environments, iterative architectures, and ambiguous problem sets in collaboration with physicists, mathematicians, and materials scientists. A strong intellectual curiosity and a track record of bridging early-stage R&D with system-level execution are essential.

Lead systems engineering for advanced technology development, integrating hardware, software, and firmware into demonstrable prototypes.

Drive architecture, requirements, and design definition in a model-based, agile engineering environment.

Partner with researchers to translate experimental goals into well-defined architectures and performance-driven system requirements.

Define and model ASIC-centric electronics systems and guide integration with broader system architectures.

Lead Preliminary and Critical Design Reviews across multi-disciplinary teams (HW, SW, ASIC, FPGA).

Work with design teams to optimize analog ASICs for signal integrity, timing, power, and noise-sensitive outputs.

Decompose experimental objectives into functional block diagrams, partitioning logic across ASICs, FPGAs, CPUs, and GPUs to meet performance targets (e.g., noise, latency, thermal).

Generate detailed interconnect and system interface diagrams for hardware and embedded platforms, defining electrical, mechanical, and data specifications.

Identify custom or COTS IP needs for analog and mixed-signal ASIC development based on experimental functionality.

~70% experience in ASIC design & implementation; ~30% in system engineering and architecture.

15+ years of ASIC, FPGA, and firmware design experience; extensive background in analog/mixed-signal systems.

Minimum of one full mixed-signal ASIC lifecycle, from concept to tape-out.

Expertise in noise mitigation, power distribution network (PDN) design, and analog performance optimization.

Strong system integration background, including architecture definition, requirements, and cross-discipline collaboration.

Skilled communicator with experience translating research needs into engineering artifacts.

Proven leadership in technical execution, from concept through integration and test.

Preferred: Experience with multi-layer PCB design and analog/mixed-signal ASICs in low-noise environments.

Bachelor's, Master's, or Doctorate in Electrical Engineering, Computer Engineering, Physics, Mathematics, or a related technical discipline from an accredited institution.

Must hold or be eligible for a Tier 5 (T5) security clearance (formerly SSBI). U.S. Citizenship required. Continuous Evaluation (CE) enrollment may be required.

The base salary range for this full-time position is $204,665 - $262,243 + bonus + benefits.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process. Please note that the compensation details listed reflect the base salary only, and do not include potential bonus or benefits.

We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing.