Principal/Senior GPU Software Performance Engineer - Training at Scale

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Principal / Senior GPU Software Performance Engineer - Training at Scale

THE ROLE:

We train large models across multiGPU clusters. Your charter is to make training materially faster and cheaper by leading kernellevel performance engineering-from math kernels and fused epilogues to clusterlevel throughput-partnering with researchers, framework teams, and infrastructure.

KEY RESPONSIBILITIES:

• Own kernel performance: Design, implement, and land highimpact HIP/C++ kernels (e.g., attention, layernorm, softmax, GEMM/epilogues, fused pointwise) that are wavesize portable and optimized for LDS, caches, and MFMA units.
• Lead profiling & tuning: Build repeatable workflows with timelines, hardware counters, and roofline analysis; remove memory bottlenecks; tune launch geometry/occupancy; validate speedups with A/B harnesses.
• Drive fusion & algorithmic improvements: Identify profitable fusions, tiling strategies, vectorized I/O, sharedmemory/scratchpad layouts, asynchronous pipelines, and warp/wavelevel collectives-while maintaining numerical stability.
• Influence frameworks & libraries: Upstream or extend performancecritical ops in PyTorch/JAX/XLA/Triton; evaluate and integrate vendor math libraries; guide compiler/codegen choices for target architectures
• Scale beyond one GPU: Optimize P2P and collective comms, overlap compute/comm, and improve data/pipeline/tensor parallelism throughput across nodes

• Benchmarking & SLOs: Define and own KPIs (throughput, timetotrain, $/step, energy/step); maintain dashboards, perf CI gates, and regression triage
• Technical leadership: Mentor senior engineers, set coding/perf standards, lead performance "war rooms," and partner with silicon/vendor teams on microarchitectureaware optimizations
• Quality & reliability: Build reproducible perf harnesses, deterministic test modes, and documentation/playbooks so improvements persist releaseoverrelease

PREFERRED EXPERIENCE:

• Experience in systems/HPC/ML performance engineering, with handson GPU kernel work and shipped optimizations in production training or HPC

• Expert in modern C++ (C++17+) and at least one GPU programming model (CUDA, HIP, or SYCL/oneAPI) or a GPU kernel DSL (e.g., Triton); comfortable with templates, memory qualifiers, atomics, and warp/wavelevel collectives
• Deep understanding of GPU microarchitecture: SIMT execution, occupancy vs. register/scratchpad pressure, memory hierarchy (global/L2/shared or LDS), coalescing, bank conflicts, vectorization, and instructionlevel parallelism
• Proficiency with profiling & analysis: timelines and counters (e.g., Nsight Systems/Compute, rocprof/Omniperf, VTune/GPA or equivalents), ISA/disassembly inspection, and correlating metrics to code changes
• Proven track record reducing timetotrain or $perstep via kernel and collectivecomms optimizations on multiGPU clusters
• Strong Linux fundamentals (perf/eBPF, NUMA, PCIe/links), build systems (CMake/Bazel), Python, and containerized dev (Docker/Podman)

• Experience with distributed training (PyTorch DDP/FSDP/ZeRO/DeepSpeed or JAX) and GPU collectives
• Expertise in mixed precision (BF16/FP16/FP8), numerics, and stability/accuracy validation at kernel boundaries
• Background in compiler/IR (LLVM/MLIR) or codegen for GPU backends; ability to guide optimization passes with performance goals
• Handson with cluster orchestration (Slurm/Kubernetes), IB/RDMA tuning, and compute/communication overlap strategies

ACADEMIC CREDENTIALS:

• Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

LOCATION:

San Jose, CA

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