Sr. Staff ASIC Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

Join our team developing next-generation graphics and compute technologies at AMD as an ASIC Design Engineer. As part of the front-end design/integration team, you will work closely with the Architecture, IP Design, Physical Design, and Product Engineering teams to deliver high-quality silicon and achieve first-pass silicon success.

THE PERSON:

The successful candidate will work closely with senior silicon design engineers. The ideal candidate will be highly detail-oriented and possess strong communication and problem-solving skills.

KEY RESPONSIBILITIES:

• Participate in all stages of the design flow, from RTL development through GDS implementation.
• Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
• Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
• Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
• Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.
• Partner with cross-functional teams across multiple engineering disciplines and geographic locations.
• Communicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.

PREFERRED EXPERIENCE:

• Strong understanding of different design stages from RTL to GDS implementation
• Proficient in RTL design implementation of Digital/Analog blocks using Verilog/System Verilog.
  Experience with HBM, D2D, Serdes, PCIe like protocols.
• Knowledge in VLSI design, Design Automation, and IC design.
• Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis.
• Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
• Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
• Basic understanding of FPGA architecture and customer usage model is a plus.
• Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
• Excellent written and verbal communication skills in English.
• Self-motivated team worker with ability to work in a fast-paced work environment.

ACADEMIC CREDENTIALS:

• Bachelor's or master's degree in computer engineering, electrical engineering, or a related field.

LOCATION:

San Jose, CA (Hybrid)

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.